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W28V400B/t 4m(512k 8/256k 16) smartvoltage flash memory publication release date: april 11, 2003 - 1 - revision a4 table of contents- 1. general d escription ......................................................................................................... ......... 3 2. features .................................................................................................................... ..................... 3 3. product overview ............................................................................................................ .......... 4 4. block diagram ............................................................................................................... ............... 5 5. pin conf igurati on ........................................................................................................... ............ 6 6. pin des cription ............................................................................................................. ................ 7 7. principles of operation ..................................................................................................... ...... 8 data prot ection ................................................................................................................ ................ 8 8. bus o peration ............................................................................................................... .............. 10 read ........................................................................................................................... .................... 10 output di sable ................................................................................................................. .............. 10 standby ........................................................................................................................ .................. 10 deep power-dow n ................................................................................................................ .......... 10 read identifier c odes oper ation ................................................................................................ ... 11 write .......................................................................................................................... ..................... 11 9. command de finiti ons ......................................................................................................... ....... 11 read array command ............................................................................................................. ...... 13 read identifier codes co mmand .................................................................................................. .13 read status regi ster co mmand ................................................................................................... 14 clear status r egister command .................................................................................................. .14 block eras e command ............................................................................................................ ...... 14 word/byte wri te co mmand ........................................................................................................ ... 15 block erase su spend comm and ................................................................................................... 1 5 word/byte write suspend co mmand ............................................................................................ 16 considerations of su spend ...................................................................................................... ...... 16 block locking .................................................................................................................. ............... 16 10. design co nsiderat ions ...................................................................................................... ... 22 three-line output control ...................................................................................................... ......... 22 ry/#by, block erase and wo rd/byte write polling ....................................................................... 22 power supply decoup ling ........................................................................................................ ...... 22
W28V400B/t - 2 - v pp trace on printed circuit b oards .............................................................................................. 2 2 v dd , v pp , #reset trans itions ...................................................................................................... 22 power-up/down protec tion ....................................................................................................... ..... 23 power dissi pation .............................................................................................................. ............ 23 11. electrical specifications .................................................................................................. .24 absolute maxi mum rati ngs* ...................................................................................................... .... 24 operating conditi ons ........................................................................................................... .......... 24 capacitanc e(1) ................................................................................................................. .............. 24 ac input/output test c onditions ................................................................................................ ... 25 dc characte ristics ............................................................................................................. ............ 27 ac characteristics - read-only operat ions(1 ) .............................................................................. 29 ac characteristics - wri te operati ons(1) ...................................................................................... 3 3 alternative #ce-controlled wri tes(1) ........................................................................................... .. 37 reset oper ations ............................................................................................................... ............ 41 block erase and word/byte write perfor mance( 3) ....................................................................... 42 12. flash memory w28v400 fa mily data pr otecti on ......................................................... 44 recommended operati ng conditi ons ............................................................................................ 45 13. ordering informat ion ....................................................................................................... .... 47 14. package di mension .......................................................................................................... ........ 47 48-lead standard thin small outline pa ckage (measured in millimeter s) ................................... 47 15. version history ............................................................................................................ ........... 48
W28V400B/t 1. general description the W28V400B/t flash memory with smartvoltage technology is a high-dens ity, cost-effective, nonvolatile, read/write storage solution for a wi de range of applications. it operates off of v dd = 2.7v and v pp = 2.7v. this low voltage operation capability realize battery life and suits for cellular phone application. its boot, parameter and main-blocked architecture, as well as low voltage and extended cycling. these features provide a highly flexible device suitable for portable terminals and personal computers. additionally, the enhanced suspend capab ilities provide an ideal solution for both code and data storage applications. for secure code stor age applications, such as networking where code is either directly executed out of flash or downloaded to dram, the device offers four levels of protection. these are: abs olute protection, enabled when v pp d v pplk ; selective hardware blocking; flexible software blocking; or write protection. these alternatives give designers comprehensive control over their code security needs . the device is manufactured on 0.35 p m process technology. it comes in industry-standard package: the 48-lead tsop, ideal for board constrained applications. 2. features x smartvoltage technology v dd = 2.7v, 3.3v or 5v v pp = 2.7v, 3.3v, 5v or 12v x user-configurable x 8 or x 16 operation x high-performance access time 85 ns (5v r 0.25v), 90 ns (5v r 0.5v), 100 ns (3.3v r 0.3v), 120 ns (2.7v to 3.6v) x operating temperature 0 q c to + 7 0 q c x optimized array blocking architecture two 4k-word (8k-by t e ) b oot b l ocks s i x 4k-word (8k-by t e ) p a ramet e r b l ocks s e v en 32k-word (64k-by t e) main b l ocks top boot location (w28v400tt) bottom boot location (W28V400Bt) x extended cycling capability minimum 100,000 block erase cycles x low power management deep power-down mode automatic power savings mode decreases i ccr in static mode x enhanced automated suspend options word/byte write suspend to read block erase suspend to word/byte write block erase suspend to read x enhanced data protection features abs o lute protec tion with v pp d v pplk block erase, full chip erase, word/byte write and lock-bit configuration lockout during power transitions b l ock b l ocks p r ot ect i on wit h #wp = v il x automated word/byte write and block erase command user interface (cui) status register (sr) x sram-compatible write interface x industry-standard packaging 48-lead tsop publ i c at i on rel e ase dat e : apri l 11, 2003 - 3 - revi si on a4
W28V400B/t - 4 - 3. product overview the W28V400B/t is a high-performance 4m-bit smartvoltage flash memory organized as 512k-byte of 8 bits or 256k-word of 16 bits. the 512k-byte/256k -word of data is arranged in two 8k-byte/4k-word boot blocks, six 8k-byte/4k-word parameter blo cks and seven 64kbyte/32k-word main blocks which are individually erasable in-system. t he memory map is shown in figure 3. smartvoltage technology provides a choice of v dd and v pp combinations, as shown in table 1, to meet system performance and power expectations. 2.7v v dd consumes approximately one-fifth the power of 5v v dd . but, 5v v dd provides the highest read performance. v pp at 2.7, 3.3v and 5v eliminates the need for a separate 12v converter, while v pp = 12v maximizes block erase and word/byte write performance. in addition to flex ible erase and program voltages, the dedicated v pp pin gives complete data protection when v pp v pplk . table 1. v dd and v pp voltage combinations offered by smartvoltage technology v dd voltage v pp voltage 2.7v 2.7v, 3.3v, 5v, 12v 3.3v 3.3v, 5v, 12v 5v 5v, 12v internal v dd and v pp detection circuitry automatically conf igures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence wri tten to the cui initiate s device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase and word/byte write operations. a block erase operation erases one of the device? s 32k-word blocks typically within 0.39s (5v v dd , 12v v pp ), 4k-word blocks typically within 0.25s (5v v dd , 12v v pp ) independent of other blocks. each block can be independently erased 100,000 times. blo ck erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in word/byte increments of the device?s 32k-word blocks typically within 8.4 p s (5v v dd , 12v v pp ), 4k-word blocks typically within 17 p s (5v v dd , 12v v pp ). word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. the boot blocks can be locked for the #wp pin. block erase or word/byte write for boot block must not be carried out by #wp to low and #reset to v ih . the status register indicates w hen the wsm?s block erase or word/b yte write operation is finished. the ry/#by output gives an additional indicator of ws m activity by providing both a hardware signal of status (versus software polling) and status ma sking (interrupt masking for background block erase, for example). status polling using ry/#by minimizes both cpu ov erhead and system power consumption. when low, ry/#by indicates that t he wsm is performing a block erase or word/byte write. ry/#by-high indicates that the wsm is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte writ e is suspended, or the device is in deep power-down mode.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 5 - revi si on a4 the access time is 85ns (t avqv ) over the commercial temperature range (0 q c to +70 q c) and v dd supply voltage range of 4.75v to 5.25v. at lower v dd voltages, the access times are 90ns (4.5v to 5.5v), 100 ns (3.0v to 3.6v) and 120 ns (2.7v to 3.6v). the automatic power savings (aps) feature substantia lly reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 1ma at v dd = 5v . when #ce and #reset pins are at v dd , the i cc cmos standby mode is enabled. when the #res e t pin is at v ss , deep power-down mode is enabled which mini mizes power consumption and provides write protection during reset. a reset time (tph qv) is required from #reset switching high until outputs are valid. lik e wis e , the devic e has a wak e ti me (tphel) from #reset-high until writes to the cui are recognized. with #reset at v ss , the wsm is reset and the status register is cleared. the device is available in 48-lead tsop (thin sma ll outline package, 1.2 mm thick). pinout is shown in figure 2. 4. block diagram y-gating 32k-word (64k-byte) main blocks x 7 output buffer dq0 -dq15 input buffer identifier register output multiplexer status register data register command user interface i/o logic data comparator a-1 input buffer address latch address counter y decoder x decoder write state machine program/erase voltage switch vdd #byte #ce #we #oe #reset #wp ry/#by vpp vdd vss a0-a17 p a ra m e te r b l o ck 0 p a ra m e te r b l o ck 1 p a ra m e te r b l o ck 2 p a ra m e te r b l o ck 3 p a ra m e te r b l o ck 4 p a ra m e te r b l o ck 5 boot bloc k 0 boot bloc k 1 m a i n b l o ck 0 m a i n b l o ck 1 m a i n b l o ck 5 m a i n b l o ck 6 figure 1. block diagram
W28V400B/t - 6 - 5. pin configuration 48-pin tsop standard pinout 12mm x 20mm top view 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 dq15/a-1 #oe a16 #ce a0 48 47 7 46 45 44 43 42 41 dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v dd dq7 dq14 dq6 dq13 dq5 dq12 dq4 #byte vss vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a9 a10 a11 a12 a13 a14 a15 24 23 a17 #we a7 a6 a5 a4 a3 a2 a1 21 22 #wp nc ry/#by #reset nc nc a8 v pp figure 2. tsop 48-lead pinout
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 7 - revi si on a4 6. pin description sym. type name and function a ? 1 a0 ? a17 input address inputs : addresses are internally latched during a write cycle. a ? 1: byte select address. not used in 16 mode. a0 ? a10: row address. selects 1 of 2048 word lines. a11 ? a14: column address. selects 1 of 16 bit lines. a15 ? a17: main block address. (boot and parameter block addresses are a12 ? a17.) dq0 ? dq15 input/ output data input/outputs : dq0 ? dq7:inputs data and commands during cui write cycles; outputs data during memory array, status register and identifier code read cycles. da ta pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dq8 ? dq15:inputs data during cui write cycles in 16 mode; outputs data during memory array read cycles in 16 mode; not used for status register and identifier code read mode. data pins float to high-impedance when the chip is deselected, outputs are disabled, or in 8 mode (#byte = v il ). data is internally latched during a write cycle. #ce input chip enable : activates the device?s control logic, input buffers, decoders and sense amplifiers. #ce-high deselects the devic e and reduces power consumption to standby levels. #reset input reset/deep power-down : puts the device in deep power-down mode and resets internal automation. #reset-high enables normal operation. when driven low, #reset inhibits write operations which provides data protection during power transiti ons. exit from deep power-down sets the device to read array mode. with #reset = v hh , block erase or word/byte write can operate to all blocks without #wp state. block erase or word/byte write with v ih < #reset < v hh produce spurious results and should not be attempted. #oe input output enable : gates the device?s outputs during a read cycle. #we input write enable : controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the #we pulse. #wp input write protect : master control for boot blocks locking. when v il, locked boot blocks cannot be erased and programmed. #byte input byte enable : #byte v il places the device in byte mode ( 8), all data is then input or output on dq0 ? 7, and dq8 ? 15 float. #byte v ih places the device in word mode ( 16), and turns off the a-1 input buffer. ry/#by output ready/#busy : indicates the status of the internal wsm. when low, the wsm is performing an internal operation (block erase or word/byte write) . ry/#by-high indicates that the wsm is ready for new commands, block erase is suspended, and word /byte write is inactive, word/byte write is suspended, or the device is in deep power-down mode. ry/#by is always active and does not float when the chip is deselected or data outputs are disabled. vpp supply block erase and word/by te write power supply : for erasing array blocks or writing words/bytes. with v pp v pplk , memory contents cannot be altered. block erase and word/byte write with an invalid v pp (see dc characteristics) produce spurious results and should not be attempted. v dd supply device power supply : internal detection configures the dev ice for 2.7v, 3.3v or 5v operation. to switch from one voltage to another, ramp v dd down to v ss and then ramp v dd to the new voltage. do not float any power pins. with v dd vlko, all write attempts to the flash memory are inhibited. device operations at invalid v dd voltage (see dc characteri stics) produce spurious results and should not be attempted. v ss supply ground : do not float any ground pins. nc no connect : lead is not internal connected; it may be driven or floated. table 1.
W28V400B/t - 8 - 7. principles of operation the W28V400B/t smartvoltage flash memory in cludes an on-chip wsm to manage block erase and word/byte write functions. it allows for 100 percent ttl-level control inputs, fixed power supplies during block erase, full chip erase, word/byte wr ite and lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from re set mode (see bus operations section), the device defaults to read array mode. manipulation of exter nal memory control pins allow array read, standby and output disable operations. status register and identifier codes can be accessed through the cui independent of the v pp voltage. high voltage on v pp enables successful block erase, word/byte writing. all functions associated with altering memory contents (block erase, word/byte wr ite, status and identifie r codes) are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui c ontents serve as input to the wsm, which controls the block erase and word /byte write. the internal algorithms are regulated by the wsm, including pulse repet ition, internal verification and margining of data. addresses and data are internally latched during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. interface software that initiates and polls progress of block erase and word/byte write can be stored in any block. this code is copied to and executed fr om system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. word/byte write suspend allows system software to suspend a word/byte write to read data from any other flash memory array location. data protection depending on the application, the system designer may choose to make the v pp power supply switchable (available only when memory block erases or word/byte writes are required) or hardwired to v pph1/2/3 . the device accommodates either design pr actice and encourages optimization of the processor-memory interface. when v pp v pplk , memory contents cannot be altered. t he cui, with two-step block erase or word/byte write command sequences, provides pr otection from unwanted operations even when high voltage is applied to v pp . all write functions are disabled when v dd is below the write lockout voltage v lko or when #reset is at v il . the device?s boot blocks locking capability for #wp provides additional protection from inadvertent code or dat a alteration by block erase and word/byte write operations. refer to table 6 for write protection alternatives.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 9 - revi si on a4 top boot bottom boot 4k-word boot block 0 4k-word boot block 1 4k-word parameter block 0 4k-word parameter block 1 4k-word parameter block 2 4k-word parameter block 3 4k-word parameter block 4 4k-word parameter block 5 32k-word main block 0 32k-word main block 1 32k-word main block 2 32k-word main block 3 32k-word main block 4 32k-word main block 5 32k-word main block 6 3ffff 38000 37fff 30000 2ffff 28000 27fff 20000 1ffff 18000 17fff 10000 0ffff 08000 07fff 07000 06fff 06000 05fff 05000 04fff 04000 03fff 03000 02fff 02000 01fff 01000 00fff 00000 4k-word boot block 0 4k-word parameter block 0 4k-word parameter block 1 4k-word parameter block 2 4k-word parameter block 3 4k-word parameter block 4 4k-word parameter block 5 32k-word main block 0 32k-word main block 1 32k-word main block 2 32k-word main block 3 32k-word main block 4 32k-word main block 5 32k-word main block 6 3ffff 3f000 3efff 3e000 3dfff 3d000 3cfff 3c000 3bfff 3b000 3afff 3a000 39fff 39000 38fff 38000 37fff 30000 2ffff 28000 27fff 20000 1ffff 18000 17fff 10000 0ffff 08000 07fff 00000 4k-word boot block 1 figure 3. memory map
W28V400B/t - 10 - 8. bus operation the local cpu reads and writes flash memory in-syste m. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. read information can be read from any block, identifie r codes or status regi ster independent of the v pp voltage. #reset can be at either v ih or v hh . the first task is to write the appropriate read mode command (read array, read identifier codes or read status register) to the cui. upon initial dev ice power-up or after exit from deep power-down mode, the device automatically resets to read array mode. six control pins dictate the data flow in and out of the component: #ce, #oe, #we, #reset , #wp and #byte. #ce and #oe must be driven active to obtain data at the outputs. #ce is the device selection control, and when active enables the selected memory device. #o e is the data output (dq0 ? dq15) control and when active drives the selected memory data onto the i/o bus. #we must be at v ih and #reset must be at v ih or v hh . figure 13, 14 illustrates read cycle. output disable with #oe at a logic-high level (v ih ), the device outputs are dis abled. output pins (dq0 ? dq15) are placed in a high-impedance state. standby setting #ce to a logic-high level (v ih ) deselects the device and places it in standby mode, which substantially reduces devic e power consumption. dq0 ? dq15 outputs are placed in a high impedance state independent of #oe. if deselected during block erase or word/byte write, the device continues functioning, and it cont inues to consume active power until the operation is completed. deep power-down setting #reset to v il initiates the deep power-down mode. in read modes, setting #reset at v il deselects the memory, places output drivers in a high- impedance state and turns off all internal circuits. #reset must be held low for a minimum of 100 ns. a delay (t phqv ) is required after return from reset until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. t he cui is reset to read array mode status register is set to 80h. during block erase or word/byte write modes, #reset at v il will abort the operation. ry/#by remains low until the reset operation is complete. memory contents at the aborted location are no longer valid since the data may be partially erased or written. a delay (t phwl ) is required after #reset goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert #reset during system reset. when the system comes out of reset, it expects to read fr om the flash memory. automated flash memories provide status information when accessed during block erase or word/byte write modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status in formation instead of array data. winbond?s flash memories allow proper cpu initializat ion following a system reset through the use of the #reset input. in this application, #reset is c ontrolled by the same #reset signal that resets the system cpu.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 11 - revi si on a4 read identifier codes operation the read identifier codes operati on outputs the manufacturer code and device code (refer to figure 4). using the manufacturer and device c odes, the system cpu can automat ically match the device with its proper algorithms. reserved for future implementation device code manufacture code [a17-a0] 3ffff 00002 00001 00000 figure 4. device identifier code memory map write writing commands to the cui enable reading of devic e data and identifier codes. they also control inspection and clearing of the status register. when v dd = v dd1/2/3/4 and used. v pp = v pph1/2/3 , the cui additionally controls block erasure and word/byte write. the block erase command requires appropriate command data and an address within the block to be erased. the word/byte write command requires the command and address of the location to be written. the cui does not occupy an addressable memory location. a write occurs when #we and #ce are active (low). the address and data needed to exec ute a command are latched on the rising edge of #we or #ce, whichever occurs first. standar d microprocessor write timings are used. figures 15 and 16 illustrate #we and #ce controlled write operations. 9. command definitions when v pp d v pplk , read operations from the status register , identifier codes, or blocks are enabled. setting v pph1/2/3 = v pp enables successful block erase and word/byte write operations. device operations are selected by writing specif ic commands into the cui. table 4 defines these commands.
W28V400B/t - 12 - table 3.1. bus operations (#byte = v ih ) (note 1, 2) mode #reset #ce #oe #we address v pp dq0 ? 15 ry/#by(3) read (note 8) v ih or v hh v il v il v ih x x d out x output disable v ih or v hh v il v ih v ih x x high z x standby (note 10) v ih or v hh v ih x x x x high z x deep power-down (note 4, 10) v il x x x x x high z v oh read identifier codes (note 8) v ih or v hh v il v il v ih see figure 4 x note 5 v oh write (note 6, 7, 8) v ih or v hh v il v ih v il x x din x table 3.2. bus operations (#byte = v il ) (note 1, 2) mode #reset #ce #oe #we address v pp dq0 ? 7 dq8 ? 15 ry/#by(3) read (note 8) v ih or v hh v il v il v ih x x d out high z x output disable v ih or v hh v il v ih v ih x x high z high z x standby (note 10) v ih or v hh v ih x x x x high z high z x deep power-down (note 4, 10) v il x x x x x high z high z v oh read identifier codes (note 8, 9) v ih or v hh v il v il v ih see figure 4 x note 5 high z v oh write (note 6, 7, 8) v ih or v hh v il v ih v il x x din x x notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2/3 for v pp . see dc characteristics for v pplk and v pph1/2/3 voltages. 3. ry/#by is v ol when the wsm is executing internal block er ase or word/byte write algorithms. it is v oh during when the wsm is not busy, in block erase suspend mode (with word/byte wr ite inactive), word/byte write suspend mode or deep power-down mode. 4. #reset at v ss 0.2v ensures the lowest deep power-down current. 5. see read identifier codes command section for details. 6. command writes involving block erase or word/byte write are reliably executed when v pp = v pph1/2/3 and v dd = v dd1/2/3/4 . block erase or word/byte write with v ih < #reset < v hh produce spurious results and should not be attempted. 7. refer to table 4 for valid din during a write operation. 8. never hold #oe low and #we low at the same timing. 9. a-1 set to v il or v ih in byte mode (#byte = v il ). 10. #wp set to v il or v ih .
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 13 - revi si on a4 table 4. command definitions (10) first bus cycle second bus cycle command bus cycles req?d. oper(1) addr(2) data(3) oper(1) addr(2) data(3) read array/reset 1 write x ffh read identifier codes 2 (note 4) write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 (note 5) write ba 20h write ba d0h word/byte write 2 (note 5, 6) write wa 40h or 10h write wa wd block erase and word/byte write suspend 1 (note 5) write x b0h block erase and word/byte write resume 1 (note 5) write x d0h notes: 1. bus operations are defined in table 3.1 and table 3.2. 2. x = any valid address within the device. ia = identifier code address: see figure 4. a-1 set to v il or v ih in byte mode (#byte = v il ). ba = address within the block being erased. the each block c an select by the address pin a17 through a12 combination. wa = address of memory location to be written. 3. srd = data read from status register. see tabl e 7 for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of #we or #ce (whichever goes high first). id = data read from identifier codes. 4. following the read identifier codes command, read operati ons access manufacturer and device codes. see read identifier codes command section for details. 5. if the block is boot block, #wp must be at v ih or #reset must be at v hh to enable block erase or word/byte write operations. attempts to issue a block erase or word/b yte write to a boot block while #wp is v ih or #reset is v ih . 6. either 40h or 10h are recognized by the wsm as the word/byte write setup. 7. commands other than those shown above are reserved by winbond for future device impl ementations and should not be used. read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase or word/byte write, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or word/byte write suspend command. the read array command functions independently of the v pp voltage and #reset can be v ih or v hh . read identifier codes command the identifier code operation is initiated by writ ing the read identifier codes command. following the command write, read cycles from addresses shown in figure 4 retrieve the manufacturer and device codes (see table 5 for identifier code values). to terminate the operation, write another valid command. like the read array command, t he read identifier codes command functions independently of the v pp voltage and #reset can be v ih or v hh . following the read identifier codes command, the following information can be read:
W28V400B/t - 14 - table 4. identifier codes code address [a17 ? a0] data [dq7 ? dq0] manufacture code 00000h b0h top boot 58h device code bottom boot 00001h 5ah read status register command the status register may be read to determine when a block erase or word/byte write is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is writt en. the status register contents are latched on the falling edge of #oe or #ce, whichever o ccurs. #oe or #ce must toggle to v ih before further reads to update the status register latch. the read status register co mmand functions independently of the v pp voltage. #reset can be v ih or v hh . clear status register command status register bits sr.5, sr.4, sr.3 or sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command. these bits indica te various failure conditions (see table 7). by allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words/bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the s equence. to clear the stat us register, the clear status register command (50h) is writt en. it functions independently of the applied v pp voltage. #reset can be v ih or v hh . this command is not functional during block erase or word/byte write suspend modes. block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase c onfirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffffh). block preconditioning, erase, and verify are handled inte rnally by the wsm (invis ible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect block erase completion by analyzing the output data of the ry/#by pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system softw are attempts corrective actions. the cui remains in read status regist er mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable block erasure can only occur when v dd = v dd1/2/3/4 and v pp = v pph1/2/3 . in the absence of this high voltage, blo ck contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". successful block erase for boot blocks requires that the corresponding if set, that #wp = v ih or #reset = v hh . if block erase is attempted to boot block when the corresponding #wp = v il or #reset = v ih , sr.1 and sr.5 will be set to "1". block erase operations with v ih < #reset < v hh produce spurious results and should not be attempted.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 15 - revi si on a4 word/byte write command word/byte write is executed by a two-cycle command sequence. word/byte write setup (standard 40h or alternate 10h) is written, followed by a sec ond write that specifies t he address and data (latched on the rising edge of #we). the wsm then takes over, controlling the word/byte write and write verify algorithms internally. after the word/byte write s equence is written, the dev ice automatically outputs status register data when can be read (see figure 6). the cpu can detect the completion of the word/byte write event by analyzing the ry/#by pin or status register bit sr.7. when word/byte write is complete, status register bit sr.4 should be checked. if word/byte write error is detected, the status r egister should be cleared. the internal ws m verify only detects errors for "1"s that do not successfully write to "0"s. the cui rema ins in read status regist er mode until it receives another command. reliable word/byte writes can only occur when v dd = v dd1/2/3/4 and v pp = v pph1/2/3 . in the absence of this high voltage, memory content s are protected against word/byte writes. if word/byte write is attempted while v pp v pplk , status register bits sr.3 and sr.4 will be set to "1". successful word/byte write for boot blocks requires that t he corresponding if set, that #wp = v ih or #reset = v hh . if word/byte write is attempted to boot block when the corresponding #wp= v il or #reset= v ih , sr.1 and sr.4 will be set to "1". word/byte write operations with v ih < #reset < v hh produce spurious results and should not be attempted. block erase suspend command the block erase suspend command allows block-erase interruption to read or word/byte write data in another block of memory. once the block-erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs st atus register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to "1"). ry/#by will also transition to v oh . specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a word/byte write command sequence can also be issued during erase suspend to program data in other blocks. using the word /byte write suspend command (see word/byte write suspend command section), a word/byte write operat ion can also be suspended. during a word/byte write operation with block erase su spended, status register bit sr.7 will return to "0" and the ry/#by output will transition to v ol . however, sr.6 will remain "1" to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and ry/#by will return to v ol . after the erase resume command is written, the device automatically outputs status register dat a when read (see figure 7). v pp must remain at v pph1/2/3 (the same v pp level used for block erase) while block erase is suspended. #reset must also remain at v ih or v hh (the same #reset level used for block erase). #wp must also remain at v il or v ih (the same #wp level used for block erase). block erase cannot resume until word/byte write operations initiated during block erase suspend have completed.
W28V400B/t - 16 - word/byte write suspend command the word/byte write suspend command allows word/byt e write interruption to read data in other flash memory locations. once the word/byte write pr ocess starts, sending the word/byte write suspend command causes the wsm to suspend the word/byte write sequence at a predetermined point in the algorithm. the device continues to output status register data w hen read after the word/byte write suspend command is written. polling status regist er bits sr.7 and sr.2 can determine when the word/byte write operation has been suspended (both will be set to "1"). ry/#by will also transition to v oh . specification t whrh1 defines the word/byte write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while word/byte write is suspended are read status register and word/byte write resume. after word /byte write resume command is written to the flash memory, the wsm will continue the word/byte writ e process. status register bits sr.2 and sr.7 will automatically clear and ry/#by will return to v ol . after the word/byte write resume command is written, the device automatica lly outputs status register data when read (see figure 8). v pp must remain at v pph1/2/3 (the same v pp level used for word/byte write) while in word/byte write suspend mode. #reset must also remain at v ih or v hh (the same #reset level used for word/byte write). #wp must also remain at v il or v ih (the same #wp level used for word/byte write). considerations of suspend after the suspend command write to the cui, read stat us register command has to write to cui, then status register bit sr.6 or sr.2 should be checked for places the device in suspend mode. block locking this boot block flash memory architecture feat ures two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. v pp = v il for complete protection the v pp programming voltage can be held low for complete write protection of all blocks in the flash device. #wp = v il for block locking the lockable blocks are locked when #wp = v il ; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. for top confi guration, the top two boot blocks are lockable. for the bottom configuration, the bottom two boot blocks are lockable. unlocked blocks can be programmed or erased normally (unless v pp is below v pplk ). #wp = v ih for block unlocking #wp = v ih unlocks all lockable blocks. these blocks can now be programmed or erased. #wp controls 2 boot blocks locking and v pp provides protection against spurious writes. table 6 defines the write protection methods.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 17 - revi si on a4 table 6. write protection alternatives operation v pp #reset #wp effect v il x x all blocks locked. v il x all blocks locked. v hh x all blocks unlocked. v il 2 boot blocks locked. block erase or word/byte write > v pplk v hh v ih all blocks unlocked. table 7. status register definition wsms ess es wbws vpps wbwss dps r 7 6 5 4 3 2 1 0 sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase status (es) 1 = error in block erase 0 = successful block erase sr.4 = word/byte write status (wbwslbs) 1 = error in word/byte write 0 = successful word/byte write sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = word/byte write suspend status (wbwss) 1 = word/byte write suspended 0 = word/byte write in progress/completed sr.1 = device protect status (dps) 1 = wp# or rp# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements (r) notes: check ry/#by or sr.7 to determine block erase or word/byte write completion. sr.6-0 are invalid while sr.7 = "0". if both sr.5 and sr.4 are "1"s after a block erase attempt, an improper command sequence was entered. sr.3 does not provide a c ontinuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase or word/byte write command sequences. sr.3 is not guaranteed to reports accurate feedback only when v pp v pph1/2/3 . the wsm interrogates the #wp and #reset only after block erase or word/byte write command sequences. it informs the system, depending on the attempted operation, if the #wp is not v ih , #reset is not v hh . sr.0 is reserved for future use and should be masked out when polling the status register.
W28V400B/t - 18 - bus operation command comments w r i t e e r a s e s e t u p data = 20h addr = within block to be erased w r i t e e r a s e c o n f i r m data = d0h addr = within block to be erased read status register data standby check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in r a d a r r a y mode. e start write 20h block erase complete read status register sr.7= full status check if desired write d0h, block address 1 0 suspend block suspend block erase erase loop no yes block address full sta t us check procedure read status register data(see above) sr.3= sr.1= sr.4,5= sr.5= block erase sucessfully 0 0 0 0 1 1 1 1 vpp range error device protect error command sequence block erase error error bus operation c ommand comments standby check sr.3 1 = v pp error detec t standby check sr.1 1 = device protect detect standby check sr.4, 5 both 1 = command sequence error standby check sr.5 1 = block erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status. register command in cases w here multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery . figure 5. automated block erase flow chart
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 19 - revi si on a4 bus operation command comments wr ite setup wor d /by t e wr ite data = 40h or 10h addr = location to be written wr ite wor d /by t e wr ite data = data to be written addr = location to be written read status register data standby check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent by te w r ites. sr full status check can be done after each word/by t e w r ite, or after a sequence of word/by t e w r ites. write ffh after the last word/by t e w r ite operation to p a c e d e v i c e i n r e a d a r r a y mode. l start write 40h or 10h, read status register sr.7= full status check if desired word/byte write complete write word/byte 1 data and adddress suspend word/byte write loop no yes write suspend word/byte 0 address full sta t us check procedure read status register data(see above) sr.3= sr.1= sr.4= 0 0 0 1 1 1 vpp range error device protect error word/byte write error word/byte write successfully bus operation command comments standby check sr.3 1 = v pp error detec t standby check sr.1 1 = device protect detect standby check sr.4 1 = data w r i t e error sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases w here multiple locations are w r itten before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery . figure 6. automated word/by t e write flow chart
W28V400B/t - 20 - start write b0h read status register sr.7= 1 0 sr.6= 0 block erase complete 1 read or word/byte write? no yes done? write d0h block erase resumed write ffh read array data word/byte write wore/byte write loop read read array data bus operation command comments wr ite erase suspend data = b0h addr = x r e a d status register data addr = x standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.6 1 = block erase suspended 0 = block erase completed wr ite erase resume data = d0h addr = x figure 7. block erase suspend/resume flow chart
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 21 - revi si on a4 word/byte write completed write d0h word/byte write resumed write ffh read array data start write b0h read status register sr.7= 1 0 sr.2= 0 1 yes done write ffh read array data reading no bus operation command comments wr ite wor d /by t e wr ite suspend data = b0h addr = x r e a d status register data addr = x standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.2 1 = word/by t e write suspended 0 = word/by t e write completed w r i t e r e a d array data = ffh addr = x r e a d read array locations other than that being w r itten. wr ite wor d /by t e wr ite resume data = d0h addr = x figure 8. word/by t e write suspend/resume flow chart
W28V400B/t - 22 - 10. design considerations three-line output control this device will often be used in large memory arrays. winbond provides three control inputs to accommodate multiple memory connections. three-line control provides for: a. lowest possible memory power dissipation. b. complete assurance that dat a bus contention will not occur. to use these control inputs efficiently, an addr ess decoder should enable #ce while #oe should be connected to all memory devices and the system?s #read control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. #reset should be connected to the system po wergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. ry/#by, block erase and word/byte write polling ry/#by is a full cmos output that provides a hardware method of detecting block erase and word/byte write completion. it transitions low after block erase or word/byte write commands and returns to v oh when the wsm has finished executing the internal algorithm. ry/#by can be connected to an interrupt input of the system cpu or controller. it is active at all times. ry/#by is also v oh when the device is in block erase su spend (with word/byte write inactive), word/byte write suspend or deep power-down modes. power supply decoupling flash memory power switching characteristics r equire careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of #ce and #oe. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected between v dd and v ss and between v pp and v ss . these high frequency, low inductance capacit ors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the array?s power supply connection between v dd and v ss . the bulk capacitor will overcome voltage drops caused by pc board trace inductance. v pp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for word/byte writing and block erasing. use similar trac e widths and layout consi derations given to the v dd power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. v dd , v pp , #reset transitions block erase and word/byte write are not guaranteed if v pp falls outside of a valid v pph1/2/3 range, v dd falls outside of a valid v dd1/2/3/4 range, or #reset v ih or v hh . if v pp error is detected, status register bit sr.3 is set to "1" along with sr.4 or sr.5, depending on the attempted operation. if #reset
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 23 - revi si on a4 transitions to v il during block erase or word/byte write, ry/#by will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially alte red. therefore, the command sequence must be repeated after normal operation is restored. de vice power-off or #reset transitions to v il clear the status register. the cui latches commands issued by syst em software and is not altered by v pp or #ce transitions or wsm actions. its state is read array mode upon powe r-up, after exit from deep power-down or after v dd transitions below v lko . after block erase or word/byte write, even after v pp transitions down to v pplk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. power-up/down protection the device is designed to offer protection against acci dental block erasure or word/byte writing during power transitions. upon power-up, the device is indifferent as to which power supply (v pp or v dd ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v dd voltages above v lko when v pp is active. since both #we and #ce must be low for a command write, driving either to v ih will inhibit writes. the cui?s two-step command sequence architecture provides added leve l of protection against data alteration. #wp provide additional protection from inadvertent code or data alteration. the device is disabled while #reset = v il regardless of its c ontrol inputs state. power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s non- volatility increases usable battery life because dat a is retained when system power is removed. in addition, deep power-down mode ensures extrem ely low power consumption even when system power is applied. for example, portable computi ng products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering #reset to v il standby or sleep modes. if access is agai n needed, the devices can be read following the t phqv and t phwl wake-up cycles required after #reset is first raised to v ih . see ac characteristics - read only and write operations and figures 13, 14, 15 and 16 for more information.
W28V400B/t - 24 - 11. electrical specifications absolute maximum ratings* operating temperature during read, block erase, and word/byte write ................................................ .......... 0 c to +70 c (1) temperature under bias .................................................................. ............................... -10 c to +80 c storage temper ature ........................................................................................................ ?65 c to +125 c voltage on any pin (except v dd , v pp and #reset) ........................................................................ ........... -0.5v to +7.0v (2) v dd supply volt age................................ ............................................................................ -0.2 v to +7.0v (2) v pp update voltage during block erase and word/byte write ........................................................... ......................... -0.2v to +14.0v (2, 3) #reset voltage .......................................................................................................... -0.5 v t o +14.0v (2, 3) output short cir cuit cu rrent .......................................................................... ......................... .......100 ma (4) *warning: stressing the device bey ond the "absolute maximum rati ngs" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "o perating conditions" may a ffect device reliability. notes: 1. operating temperature is for commercial tem perature product defined by this specification. 2. all specified voltages are with respect to v ss . minimum dc voltage is -0.5v on input/output pins and -0.2v on v dd and v pp pins. during transitions, this level may undershoot to -2.0v for periods <20 ns. maximum dc voltage on input/output pins and v dd is v dd +0.5v which, during transitions, may overshoot to v dd +2.0v for periods <20 ns. 3. maximum dc voltage on v pp and #reset may overshoot to +14.0v for periods <20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. operating conditions temperature and v dd operating conditions parameter symbol min. max. unit test condition operating temperature t a 0 +70 c ambient temperature v dd supply voltage (2.7v to 3.6v) v dd1 2.7 3.6 v v dd supply voltage (3.3v 0.3v) v dd2 3.0 3.6 v v dd supply voltage (5.0v 0.25v) v dd3 4.75 5.25 v v dd supply voltage (5.0v 0.5v) v dd4 4.50 5.50 v capacitance(1) t a = +25 c, f = 1 mhz parameter symbol typ. max. unit condition input capacitance c in 7 10 pf v in = 0.0v output capacitance c out 9 12 pf v out = 0.0v note: sampled, not 100% tested.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 25 - revi si on a4 ac input/output test conditions 2.7 0.0 input 1.35 1.35 output test points ac test i n puts are dri v en at 2.7v for a logi c "1" and 0.0v for a logi c "0". input ti mi ng begi ns, and output ti mi ng ends, at 1.3 5v. input ri se and fal l ti mes (10% to 90%) <10 ns. fi gure 9. transi ent input/output reference waveform for v dd = 2.7v to 3.6v 3.0 0.0 input 1.5 1.5 output test points ac test inputs are driven at 3.0v for a logi c "1" and 0.0v for a logic "0". input ti ming begins, and output timing ends, at 1.5 v. input ri se and fal l ti mes (10% to 90%) <10 ns. fi gure 10. transi ent input/output reference waveform for v dd = 3.3v r 0.3v and v dd = 5v r 0.25v (hi gh speed testi ng confi gurati on) 2.4 0.45 input 2.0 0.8 output test points 0.8 2.0 ac test i nputs are dri v en at v oh (2.4 v ttl ) for a logi c "1" and v ol (0.45 v ttl ) for a logi c "0." input ti mi ng begi ns at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output ti mi ng ends at v ih and v il . input ri se and fal l ti mes (10% to 90%) <10 ns. fi gure 11. transi ent input/output reference waveform for v dd = 5v r 0.5v (standard testi ng confi gurati on)
W28V400B/t - 26 - 1.3v includes jig capacitance (in914) device under test out =3.3k ohm r l c l c l fi gure 12. transi ent equi val ent testi ng load ci rcui t test configuration capacitance loading value test configuration cl(pf) v dd = 3.3v r 0.3v, 2.7v to 3.6v 30 v dd = 5v r 0.25v 30 v dd = 5v r 0.5v 100
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 27 - revi si on a4 dc characteristics v dd = 2.7v ? 3.6v v dd = 5v 0.5 parameter sym. test conditions typ. max. typ. max. unit input load current (note1) i li v dd = v dd max. v in = v dd or v ss 0.5 1 a output leakage current (note1) i lo v dd = v dd max. v out = v dd or v ss 0.5 10 a cmos level inputs v dd = v dd max. #ce = #reset = v dd 0.2v 25 50 30 100 a v dd standby current (note 1, 3, 6, 10) i ccs ttl level inputs v dd = v dd max. #ce = #reset = v ih 0.2 2 0.4 2 ma v dd reset power-down current (note 1, 10) i ccd #reset = v ss 0.2v i out (ry/#by) = 0 ma 4 10 10 a cmos inputs v dd = v dd max., #ce = v ss , f = 5 mhz (3.3v 0.3), f = 5 mhz (2.7v ? 3.6v) f = 8 mhz (5v + 0.5v) iout = 0 ma 15 25 50 ma v dd read current (note 1, 5, 6) i ccr ttl inputs v dd = v dd max., #ce = v ss , f = 5 mhz (3.3v 0.3), f = 5 mhz (2.7v ? 3.6v) f = 8 mhz (5v 0.5v), iout = 0 ma 30 65 ma v pp = 2.7v ? 3.6v 5 17 - - ma v pp = 4.5v ? 5.5v 5 17 35 ma v dd word/byte write current (note 1, 7) i ccw v pp = 11.4v ? 12.6v 5 12 30 ma v pp = 2.7v ? 3.6v 4 17 - - ma v pp = 4.5v ? 5.5v 4 17 30 ma v dd block erase current (note 1, 7) i cce v pp = 11.4v ? 12.6v 4 12 25 ma v dd word/byte write or block erase suspend current (note1, 2) i ccws i cces #ce = v ih 1 6 1 10 ma i pps v pp v dd 2 15 2 15 a v pp standby or read current (note1) i cppr v pp > v dd 10 200 10 200 a v pp deep power-down current (note1) i ppd #reset = v ss 0.2v 0.1 5 0.1 5 a v pp = 2.7v ? 3.6v 12 40 - - ma v pp = 4.5v ? 5.5v 40 40 ma v pp word/byte write current (note 1, 7) i ppw v pp = 11.4v ? 12.6v 30 30 ma v pp = 2.7v ? 3.6v 8 25 - - ma v pp = 4.5v ? 5.5v 25 25 ma v pp block erase current (note 1, 7) i ppe v pp = 11.4v ? 12.6v 20 20 ma v pp word/byte write or block erase suspend current (note 1) i ppws i ppes v pp = v pph1/2/3 10 200 10 200 a
W28V400B/t - 28 - dc characteristics (continued) v dd = 2.7v - 3.6v v dd = 5v 0.5v parameter sym. test conditions min. max. min. max. unit input low voltage (note 7) v il -0.5 0.8 -0.5 0.8 v input high voltage (note 7) v ih 2.0 v dd +0.5 2.0 v dd +0.5 v output low voltage (note 3, 7) v ol v dd = v dd min. i ol = 5.8 ma (5v 0.5v) i ol = 2.0 ma (3.3v 0.3v) i ol = 2.0 ma (2.7v ? 3.6v) 0.4 0.45 v output high voltage (ttl) (note 3, 7) v oh1 v dd = v dd min. i oh = -2.5 ma (5v 0.5v) i oh = -2.0 ma (3.3v 0.3v) i oh = -1.5 ma (2.7v ? 3.6v) 2.4 2.4 v 0.85 v dd 0.85 v dd v output high voltage (cmos) (note 3, 7) v oh2 v dd = v dd min. i oh = -2.0 ma v dd -0.4 v dd -0.4 v v pp lockout during normal operations (note 4, 7) v pplk v dd = v dd min. i oh = -100 a 1.5 1.5 v v pp during block erase or word/byte write operations v pph1 2.7 3.6 - - v v pp during block erase or word/byte write operations v pph2 4.5 5.5 4.5 5.5 v v pp during block erase or word/byte write operations v pph3 11.4 12.6 11.4 12.6 v v dd lockout voltage v lko 2.0 2.0 v #reset unlock voltage (note 8, 9) v hh unavailable #wp 11.4 12.6 11.4 12.6 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v dd voltage and t a = +25 c. 2. i ccws and i cces are specified with the device de-selected. if read or word/byte written while in erase suspend mode, the device?s current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. includes ry/#by. 4. block erases and word/byte writes are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.), between v pph1 (max.) and v pph2 (min.), between v pph2 (max.) and v pph3 (min.), and above v pph3 (max.). 5. automatic power savings (aps) reduces typical i ccr to 1ma at 5v v dd and 3 ma at 2.7v and 3.3v v dd in static operation. 6. cmos inputs are either v dd 0.2v or v ss 0.2v. ttl inputs are either v il or v ih . 7. sampled, not 100% tested. 8. boot block erases and word/byte writes are inhibited when the corresponding #reset = v ih and #wp = v il . block erase and word/byte write operations are not guaranteed with v ih < #reset < v hh and should not be attempted. 9. #reset connection to a v hh supply is allowed for a maximum cumulative period of 80 hours. 10. #byte input level is v dd 0.2v in word mode or v ss 0.2v in byte mode. #wp input level is v dd 0.2v or v ss 0.2v.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 29 - revi si on a4 ac characteristics - read-only operations(1) v dd = 2.7v to 3.6v, t a = 0 c to +70 c parameter sym. min. max. unit read cycle time t avav 120 ns address to output delay t avqv 120 ns #ce to output delay (note 2) t elqv 120 ns #reset high to output delay t phqv 600 ns #oe to output delay (note 2) t glqv 50 ns #ce to output in low z (note 3) t elqx 0 ns #ce high to output in high z (note 3) t ehqz 55 ns #oe to output in low z (note 3) t glqx 0 ns #oe high to output in high z (note 3) t ghqz 20 ns output hold from address ? , #ce or #oe change, whichever occurs first (note 3) t oh 0 ns #byte to output delay (note 3) t fvqv 120 ns #byte low to output in high z (note 3) t flqz 30 ns #ce to #byte high or low (note 3, 6) t elfv 5 ns notes: see 5.0v v dd read-only operations for notes 1 through 6. v dd = 3.3v 0.3v, t a = 0 c to +70 c parameter sym. min. max. unit read cycle time t avav 100 ns address to output delay t avqv 100 ns #ce to output delay (note 2) t elqv 100 ns #reset high to output delay t phqv 600 ns #oe to output delay (note 2) t glqv 50 ns #ce to output in low z (note 3) t elqx 0 ns #ce high to output in high z (note 3) t ehqz 55 ns #oe to output in low z (note 3) t glqx 0 ns #oe high to output in high z (note 3) t ghqz 20 ns output hold from address, #ce or #oe change, whichever occurs first (note 3) t oh 0 ns #byte to output delay (note 3) t fvqv 100 ns #byte low to output in high z (note 3) t flqz 30 ns #ce to #byte high or low (note 3, 6) t elfv 5 ns note: see 5.0v v dd read-only operations for notes 1 through 6.
W28V400B/t - 30 - v dd = 5v 0.5v, 5v 0.25v, t a = 0 c to +70 c v dd = 5v 0.25v (4) 5v 0.5v (5) unit parameter sym. min. max. min. max. read cycle time t avav 85 90 ns address to output delay t avqv 85 90 ns #ce to output delay (note 2) t elqv 85 90 ns #reset high to output delay t phqv 400 400 ns #oe to output delay (note 2) t glqv 40 45 ns #ce to output in low z (note 3) t elqx 0 0 ns #ce high to output in high z (note 3) t ehqz 55 55 ns #oe to output in low z (note 3) t glqx 0 0 ns #oe high to output in high z (note 3) t ghqz 10 10 ns output hold from address, #ce or #oe change, whichever occurs first (note 3) t oh 0 ns #byte to output delay (note3) t fvqv 85 90 ns #byte low to output in high z (note 3) t flqz 25 30 ns #ce to #byte high or low (note 3, 6) t elfv 5 5 ns notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. #oe may be delayed up to t elqv to t glqv after the falling edge of #ce without impact on t elqv . 3. sampled, not 100% tested. 4. see transient input/output reference waveform and transient equivalent testing load circuit (high speed configuration) for testing characteristics. 5. see transient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics. 6. if #byte transfer during reading cycle, exist the regulations separately.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 31 - revi si on a4 v ih v il address(a) #oe(g) #we(w) #ce(e) t ghqz v ih v il standby device address selection data valid address stable v ih v il v ih v il t ehqz v ih v il data(d/q) (dq0-dq15) v oh v ol v dd #reset(p) high z high z t glqv t elqv t elqx t glqx t oh valid output t avav t avqv t phqv fi gure 13. ac waveform for read operati ons
W28V400B/t - 32 - address(a) #oe(g) #byte(f) #ce(e) t ghqz v ih v il standby device address selection data valid address stable v ih v il v ih v il t ehqz v ih v il v v high z t glqx t oh data(d/q) (dq0-dq7) oh ol high z data output t avav t flqz t glqv t fvqv valid output data(d/q) (dq0-dq7) oh ol high z v v data output high z t elqx t elfv t elqv t avqv fi gure 14. #by t e ti mi ng waveform
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 33 - revi si on a4 ac characteristics - write operations(1) v dd = 2.7v to 3.6v, t a = 0 c to +70 c parameter sym. min. max. unit write cycle time t avav 120 ns #reset high recovery to #we going low (note 2) t phwl 1 s #ce setup to #we going low t elwl 10 ns #we pulse width t wlwh 50 ns #reset v hh setup to #we going high (note 2) t phhwh 100 ns #wp v ih setup to #we going high (note 2) t shwh 100 ns v pp setup to #we going high (note 2) t vpwh 100 ns address setup to #we going high (note 3) t avwh 50 ns data setup to #we going high (note 3) t dvwh 50 ns data hold from #we high t whdx 0 ns address hold from #we high t whax 5 ns #ce hold from #we high t wheh 10 ns #we pulse width high t whwl 30 ns #we high to ry/#by going low t whrl 100 ns write recovery before read t whgl 0 ns v pp hold from valid srd, ry/#by high (note 2, 4) t qvvl 0 ns #reset v hh hold from valid (note 2, 4) t qvph 0 ns #wp v ih hold from valid srd, ry/#by high (note 2, 4) t qvsl 0 ns #byte setup to #we going high (note 7) t fvwh 50 ns #byte hold from #we high (note 7) t whfv 120 ns note: see 5.0v v dd ac characteristics - write operations for notes 1 through 7.
W28V400B/t - 34 - v dd = 3.3v 0.3v, t a = 0 c to +70 c parameter sym. min. max. unit write cycle time t avav 100 ns #reset high recovery to #we going low (note 2) t phwl 1 s #ce setup to #we going low t elwl 10 ns #we pulse width t wlwh 50 ns #reset v hh setup to #we going high (note 2) t phhwh 100 ns #wp v ih setup to #we going high (note 2) t shwh 100 ns v pp setup to #we going high (note 2) t vpwh 100 ns address setup to #we going high (note 3) t avwh 50 ns data setup to #we going high (note 3) t dvwh 50 ns data hold from #we high t whdx 0 ns address hold from #we high t whax 5 ns #ce hold from #we high t wheh 10 ns #we pulse width high t whwl 30 ns #we high to ry/#by going low t whrl 100 ns write recovery before read t whgl 0 ns v pp hold from valid srd, ry/#by high (note 2, 4) t qvvl 0 ns #reset v hh hold from valid (note 2, 4) t qvph 0 ns #wp v ih hold from valid srd, ry/#by high (note 2, 4) t qvsl 0 ns #byte setup to #we going high (note 7) t fvwh 50 ns #byte hold from #we high (note 7) t whfv 100 ns note: see 5.0v v dd ac characteristics - write operations for notes 1 through 7.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 35 - revi si on a4 v dd = 5v 0.5v, 5v 0.25v, t a = 0 c to +70 c 5v 0.25v (5) 5v 0.5v (6) unit parameter sym. min. max. min max. write cycle time t avav 85 90 ns #reset high recovery to #we going low (note 2) t phwl 1 1 s #ce setup to #we going low t elwl 10 10 ns #we pulse width t wlwh 40 40 ns #reset v hh setup to #we going high (note 2) t phhwh 100 100 ns #wp v ih setup to #we going high (note 2) t shwh 100 100 ns v pp setup to #we going high (note 2) t vpwh 100 100 ns address setup to #we going high (note 3) t avwh 40 40 ns data setup to #we going high (note 3) t dvwh 40 40 ns data hold from #we high t whdx 0 0 ns address hold from #we high t whax 5 5 ns #ce hold from #we high t wheh 10 10 ns #we pulse width high t whwl 30 30 ns #we high to ry/#by going low t whrl 90 90 ns write recovery before read t whgl 0 0 ns v pp hold from valid srd, ry/#by high (note 2, 4) t qvvl 0 0 ns #reset v hh hold from valid srd, ry/by# high (note 2, 4) t qvph 0 0 #wp v ih hold from valid srd, ry/#by high (note 2, 4) t qvsl 0 0 ns #byte setup to #we going high (note 7) t fvwh 40 40 ns #byte hold from #we high (note 7) t whfv 85 90 ns notes: 1. read timing characteristics during block erase and word/byte write operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 4 for valid ain and din for block erase or word/byte write. 4. v pp should be held at v pph1/2/3 (and if necessary #reset should be held at v hh ) until determination of block erase or word/byte write success (sr.1/3/4/5 = 0). 5. see transient input/output reference waveform and transient equivalent testing load circuit (high seed configuration) for testing characteristics. 6. see transient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics. 7. if #byte switch during reading cycle, exist the regulations separately.
W28V400B/t - 36 - address(a) #oe(g) #we(w) #ce(e) v ih v il v ih v il v ih v il t wlwh t whqv1,2 data(d/q) v ih high z t whgl #byte(f) ih v il v v ih v il a in a in t avav elwl t wheh t t avwh t whax t whwl t dvwh t whdx d in d in valid srd d in t phwl t fvwh t whfv ry/#by(r) v il v ol t whrl #wp(s) ih il v v t shwh t qvsl t #reset(p) ih il v v vpwh t pph3,2,1 v pplk v il v qvvl t (v) v pp 1 2 3 4 5 6 hh v phhwh t qvph t oh v fi gure 15. ac waveform for #we-control l ed wri t e operati ons notes: 1. v dd pow er-up and standby . 2. wri t e bl ock erase or w o rd/by t e w r i t e setup. 3. wri t e bl ock erase confi r m or val i d address and data. 4. automated erase or program del ay . 5. read status regi ster data. 6. wri t e read array command.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 37 - revi si on a4 alternative #ce-controlled writes(1) v dd = 2.7v to 3.6v, t a = 0 c to +70 c parameter sym. min. max. unit write cycle time t avav 120 ns #reset high recovery to #ce going low (note 2) t phel 1 s #we setup to #ce going low t wlel 0 ns #ce pulse width t eleh 70 ns #reset v hh setup to #ce going high (note 2) t phheh 100 ns #wp v ih setup to #ce going high (note 2) t sheh 100 ns v pp setup to #ce going high (note 2) t vpeh 100 ns address setup to #ce going high (note 3) t aveh 50 ns data setup to #ce going high (note 3) t dveh 50 ns data hold from #ce high t ehdx 0 ns address hold from #ce high t ehax 5 ns #we hold from #ce high t ehwh 0 ns #ce pulse width high t ehel 25 ns #ce high to ry/#by going low t ehrl 100 ns write recovery before read t ehgl 0 ns v pp hold from valid srd, ry/#by high (note 2, 4) t qvvl 0 ns #reset v hh hold from valid srd, ry/#by high (note 2, 4) t qvph 0 ns #wp v ih hold from valid srd, ry/#by high (note 2, 4) t qvsl 0 ns #byte setup to #ce going high (note 7) t fveh 50 ns #byte hold from #ce high (note 7) t ehfv 120 ns note: see 5.0v v dd alternative #ce-controlled writes for notes 1 through 7.
W28V400B/t - 38 - v dd = 3.3v 0.3v, t a = 0 c to +70 c parameter sym. min. max. unit write cycle time t avav 100 ns #reset high recovery to #ce going low (note 2) t phel 1 s #we setup to #ce going low t wlel 0 ns #ce pulse width t eleh 70 ns #reset v hh setup to #ce going high (note 2) t phheh 100 ns #wp v ih setup to #ce going high (note 2) t sheh 100 ns v pp setup to #ce going high (note2) t vpeh 100 ns address setup to #ce going high (note 3) t aveh 50 ns data setup to #ce going high (note 3) t dveh 50 ns data hold from #ce high t ehdx 0 ns address hold from #ce high t ehax 5 ns #we hold from #ce high t ehwh 0 ns #ce pulse width high t ehel 25 ns #ce high to ry/#by going low t ehrl 100 ns write recovery before read t ehgl 0 ns v pp hold from valid srd, ry/#by high (note 2, 4) t qvvl 0 ns #reset v hh hold from valid srd, ry/#by high (note 2, 4) t qvph 0 ns #wp v ih hold from valid srd, ry/#by high (note 2, 4) t qvsl 0 ns #byte setup to #ce going high (note 7) t fveh 50 ns #byte hold from #ce high (note 7) t ehfv 100 ns note: see 5.0v v dd alternative #ce-controlled writes for notes 1 through 7.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 39 - revi si on a4 v dd = 5v 0.5v, 5v 0.25v, t a = 0 c to +70 c v dd = 5v 0.25v (5) 5v 0.5v (6) parameter sym. min. max. min. max. unit write cycle time t avav 85 90 ns #reset high recovery to #ce going low (note 2) t phel 1 1 s #we setup to #ce going low t wlel 0 0 ns #ce pulse width t eleh 50 50 ns #reset v hh setup to #ce going high (note 2) t phheh 100 100 ns #wp v ih setup to #ce going high (note 2) t sheh 100 100 ns v pp setup to #ce going high (note 2) t vpeh 100 100 ns address setup to #ce going high (note 3) t aveh 40 40 ns data setup to #ce going high (note 3) t dveh 40 40 ns data hold from #ce high t ehdx 0 0 ns address hold from #ce high t ehax 5 5 ns #we hold from #ce high t ehwh 0 0 ns #ce pulse width high t ehel 25 25 ns #ce high to ry/#by going low t ehrl 90 90 ns write recovery before read t ehgl 0 0 ns v pp hold from valid srd, ry/#by high (note 2, 4) t qvvl 0 0 ns #reset v hh hold from valid srd, ry/#by high (note 2, 4) t qvph 0 0 ns #wp v ih hold from valid srd, ry/#by high (note 2, 4) t qvsl 0 0 ns #byte setup to #ce going high (note 7) t fveh 40 40 ns #byte hold from #ce high (note 7) t ehfv 85 90 ns notes: 1. in systems where #ce defines the write pulse width (within a longer #we timing waveform), all setup, hold, and inactive #we times should be measured relative to the #ce waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid ain and din for block erase or word/byte write. 4. v pp should be held at v pph1/2/3 (and if necessary #reset should be held at v hh ) until determination of block erase or word/byte write success (sr.1/3/4/5 = 0). 5. see transient input/output reference waveform and transient equivalent testing load circuit (high seed configuration) for testing characteristics. 6. see transient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics. 7. if #byte switch during reading cycle, exist the regulations separately.
W28V400B/t - 40 - address(a) #oe(g) #we(w) #ce(e) v ih v il v ih v il v ih v il t wlel data(d/q) v ih high z t ehgl #byte(f) ih il v v v ih v il a in a in t avav eleh t ehel t t aveh t ehax t ehdx d in d in valid srd d in t phel t fveh t ehfv ry/#by(r) v il v ol t ehrl #wp(s) ih il v v t sheh t qvsl t #reset(p) ih il v v (v) vpeh t pph3,2,1 v pplk v il v qvvl t v pp 1 2 3 4 5 6 t ehwh t ehqv1,2 dveh t phheh t qvph t v hh oh v fi gure 16. ac waveform for #ce-control l ed wri t e operati ons notes: 1. v dd pow er-up and standby . 2. wri t e bl ock erase or w o rd/by t e w r i t e setup. 3. wri t e bl ock erase confi r m or val i d address and data. 4. automated erase or program del ay . 5. read status regi ster data. 6. wri t e read array command.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 41 - revi si on a4 reset operations ry/#by(r) ih il v v #reset(p) plph t (a)reset during read array mode ( c ) #reset risin g timin g 2.7v/3.3v/5v v il ih il v v #reset(p) 235vph t ry/#by(r) ih il v v #reset(p) plph t (b)reset during block erase, full chip erase, word/byte write or lock-bit configuration plrh t v dd v ol v oh v ol v oh fi gure 17. ac waveform for reset operati on reset ac specifications v dd = 2.7v 3.6v v dd = 3.0v 3.6v v dd = 4.5v 5.5v s y m . p a ra m e t e r m i n . m a x . m i n . m a x . m i n . m a x . unit t plph #reset pulse low t i me (if rp# is tied to v dd, this specification is not applicable) 1 0 0 1 0 0 1 0 0 n s t plrh #reset low to reset during block erase or w o rd/by t e w r ite (note 1, 2) 2 2 2 0 1 2 p s t 235vph v dd 2.7v to #reset high v dd 3.0v to #reset high v dd 4.5v to #reset high (note 3) 1 0 0 1 0 0 1 0 0 n s notes: 1. if #reset is asserted w h ile a block erase or w o rd/by t e w r ite operation is not ex ecuting, the reset w ill complete w i thin 100n s. 2. a reset time, t ph qv , is required from the later of ry /#by or #reset going high until outputs are valid. 3. when the device pow er-up, holding #reset low minimum 100 ns is required after v dd has been i n predefi ned range and al so has been i n stabl e there.
W28V400B/t - 42 - block erase and word/byte write performance(3) v dd = 2.7v to 3.6v, t a = 0 c to +70 c v pp = 2.7v ? 3.6v v pp = 4.5v ? 5.5v v pp = 11.4v ? 12.6 v sym. parameter note typ.(1) max. typ.(1) max. typ.(1) max. unit 32k word block 2 44.6 17.7 12.6 s word/byte write time 4k word block 2 45.9 26.1 24.5 s 32k word block 2, 4 1.46 0.58 0.42 s t whqv1 t ehqv1 block write time 4k word block 2, 4 0.19 0.11 0.11 s 32k word block 2 1.14 0.61 0.51 s t whqv2 t ehqv2 block erase time 4k word block 2 0.38 0.32 0.31 s t whrh1 t ehrh1 word/byte write suspend latency time to read 7 8 6 8 6 7 s t whrh2 t ehrh2 erase suspend latency time to read 18 22 11 14 11 14 s note: see 5v v dd block erase and word/byte write performance for notes 1 through 4. v dd = 3.3v 0.3v, t a = 0 c to +70 c v pp = 2.7v ? 3.6v v pp = 4.5v ? 5.5v v pp = 11.4v ? 12.6v sym. parameter note typ.(1) max. typ.(1) max. typ.(1) max. unit 32k word block 2 44 17.3 12.3 s word/byte write time 4k word block 2 45 25.6 24 s 32k word block 2, 4 1.44 0.57 0.41 s t whqv1 t ehqv1 block write time 4k word block 2, 4 0.19 0.11 0.1 s 32k word block 2 1.11 0.59 0.5 s t whqv2 t ehqv2 block erase time 4k word block 2 0.37 0.31 0.3 s t whrh1 t ehrh1 word/byte write suspend latency time to read 6 7 5 7 5 6 s t whrh2 t ehrh2 erase suspend latency time to read 16.2 20 9.6 12 9.6 12 s note: see 5v v dd block erase and word/byte write performance for notes 1 through 4.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 43 - revi si on a4 v dd = 5v 0.5v, 5v 0.25v, t a = 0 c to +70 c v pp = 4.5v ? 5.5v v pp = 11.4v ? 12.6v sym. parameter note typ.(1) max. typ.(1) max. unit 32k word block 2 12.2 8.4 s word/byte write time 4k word block 2 18.3 17 s 32k word block 2, 4 0.4 0.28 s t whqv1 t ehqv1 block write time 4k word block 2, 4 0.08 0.07 s 32k word block 2 0.46 0.39 s t whqv2 t ehqv2 block erase time 4k word block 2 0.26 0.25 s t whrh1 t ehrh1 word/byte write suspend latency time to read 5 6 4 5 s t whrh2 t ehrh2 erase suspend latency time to read 9.6 12 9.6 12 s notes: 1. typical values measured at t a = +25 c and nominal voltages. subject to change based on device characterization. 2. excludes system-level overhead. 3. sampled but not 100% tested. 4. all values are in word mode (#byte = v ih ). at byte mode (#byte = v il ), those values are double.
W28V400B/t - 44 - 12. flash memory w28v400 family data protection noises having a level exceeding the limit specifi ed in this document may be generated under specific operating conditions on some systems. such noises, when induced onto #we signal or power supply, may be interpreted as false commands, and which will cause undesired memory updating. to protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the followi ng write protect designs, as appropriate: 1. protecting data in specific block by setting a #wp to low, only the boot bl ock can be protected against overwriting. parameter and main blocks cannot be locked. system program, etc., can be locked by storing them in the boot block. when a high voltage is applied to #reset, overwrite operation is enabled for all blocks. 2. data protection through v pp when the level of v pp is lower than v pplk (lockout voltage), write operation on the flash memory is disabled. all blocks are locked and the data in the blocks are completely write protected. 3. data protection through #reset when the #reset is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. 4. noise rejection of #we consider noise rejection of #we in or der to prevent false write command input.
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 45 - revi si on a4 recommended operating conditions at device pow e r-up ac timing illustrated in figure 18 is recommended fo r the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. v ih v il dd v ih v il v ih v il #oe valid address v dd v vss (min) t vr t r t 2vph t phqv *1 #reset (p) *2 vpp (v) vss v pph1/2 a ddress v ih v il (a) t t r or f t t r or f t avqv #ce (e) t r t f t elqv t glqv #we (w) v ih v il (g) t f t r #wp (s) v ih v il data (d/q) v oh v ol valid output high z *1 t 5vph for the devi c e i n 5v operati ons. *2 to prevent the unw anted w r i t es, sy stem desi gners shoul d consi der the v pp sw i t ch, w h i c h connects v pp to v ss duri ng read operati ons and v pph1/2/3 duri ng w r i t e or erase operati ons. fi gure 18. ac ti mi ng at devi ce pow e r-up for the ac speci f i c ati ons t vr , t r , t f in the figure, refer to the next page. see the ?electrical specificatio ns? described in speci f i c ati ons for the suppl y vol t age range, the operati ng temper ature and the ac speci f i c ati ons not show n i n the next page.
W28V400B/t - 46 - rise and fall time pa ra m e t e r s y m b o l m i n . ma x . u n i t v dd rise time (note 1) t vr 0 . 5 3 0 0 0 0 p s/ v input signal rise time (note 1, 2) t r 1 p s/ v input signal fall time (note 1, 2) t f 1 p s/ v notes: 1. sampl ed, not 100% tested. 2. thi s speci f i c ati on i s appl i ed for not onl y t he devi c e pow er-up but al so the normal operati ons. t r (max.) and t f (max .) for #reset are 100 p s/v glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure 19 (b). the acceptable glitch noises are illustrated in figure 19 (a). input singal v ih (min.) input singal v ih (min.) v il (max.) input singal v il (max.) input singal ( a ) acce p table glitch noises (b) not acceptable glitch noises fi gure 19. waveform for gl i t ch noi s es see the "dc characteristics" descri bed i n speci f i c ati ons for v ih (mi n .) and v il (max .).
W28V400B/t publ i c at i on rel e ase dat e : apri l 11, 2003 - 47 - revi si on a4 13. ordering information part no. access time (ns) operating temperature ( q c) boot block package w 2 8 v 4 0 0 b t 8 5 c 8 5 0 70 bottom boot 48l tsop w 2 8 v 4 0 0 t t 8 5 c 8 5 0 70 top boot 48l tsop notes: 1. wi nbond reserves the ri ght to make changes to i t s products w i thout pri o r noti c e. 2. purchasers are responsi b l e for performi ng appropri a te qual i t y assurance testi ng on products i n tended for use i n appl i c ati ons w here personal i n j u ry mi ght occur as a consequence of product fai l u re. 14. package dimension 48-lead standard thin small outline package (measured in millimeters) 0.020 0.004 0.005 0.035 0.003 min. 0.50 y l l1 c 0.35 0.10 0.65 0.21 millimeter a a2 b a1 0.90 0.12 0.075 sym. min. 1.20 0.28 1.10 1.00 0.20 max. nom. 0.032 0.008 0.026 0.017 0.043 0.047 0.011 0.039 nom. inch max. e h d 0 8 0 8 e d 18.2 18.4 18.6 19.7 20.0 20.3 11.8 12.0 12.2 0.718 0.724 0.730 0.775 0.787 0.799 0.466 0.472 0.478 0.10 0.80 0.031 0.004 0.020 0.50 t e 1 48 b e d y a1 a a2 l1 l c h d t 0.125 0.175 0.005 0.007
W28V400B/t - 48 - 15. version history v e r s i o n d a t e p a g e d e s c r i p t i o n a1 may 22, 2002 - initial issued a2 aug. 5, 2002 all update descriptions and correct typo a3 nov. 18, 2002 45 correct the typo in figure 18 a4 apr. 11, 2003 all update descriptions and correct typo headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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